This invention relates to programmable logic array integrated circuit devices (xe2x80x9cprogrammable logic devicesxe2x80x9d or xe2x80x9cPLDsxe2x80x9d), and more particularly to interconnection resources for use on programmable logic devices that increase the speed at which those devices can be made to operate. The invention also relates to such other features of PLDs as secondary signal (e.g., clock and clear signal) distribution, input/output circuitry, and cascade connections between logic modules.
Programmable logic devices typically include (1) many regions of programmable logic, and (2) programmable interconnection resources for selectively conveying signals to, from, and/or between those logic regions. Each logic region is programmable to perform any of several different, relatively simple logic functions. The interconnection resources are programmable to allow the logic regions to work together to perform much more complex logic functions than can be performed by any individual logic region. Examples of known PLDs are shown in Wahlstrom U.S. Pat. No. 3,473,160, Freeman U.S. Patent Re. No. 34,363, Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, and Jefferson et al. U.S. Pat. No. 6,215,326, all of which are hereby incorporated by reference herein in their entireties.
A typical measure of the maximum speed at which a PLD can be made to operate is the longest time required for a signal to propagate through the device from the register of any logic region (or other resource with a register) to the register of any other logic region (or other resource with a register). A PLD cannot be safely clocked at a clock rate having a period less than this longest signal propagation time. An important design objective for most PLDs is to minimize the longest signal propagation time. Thus both the logic regions and the interconnection resources are typically designed to be time-efficient in this respect. Once this has been done, however, for a given integrated circuit fabrication technology, it is difficult to significantly further reduce the longest signal propagation time. For example, to increase the speed of interconnection resources, bigger drivers and pass transistors can be used, but the corresponding diffusion loading on the routing channels will also increase. Wider metal tracks can be used for interconnection conductors to reduce metal RC delay, but this will increase die size substantially. As a result, the final speed-up is diminished.
In view of the foregoing, it is an object of this invention to provide improved programmable logic devices.
It is a more particular object of this invention to provide improved interconnection resources for programmable logic devices.
It is a still more particular object of this invention to provide interconnection resources for programmable logic devices which reduce the longest signal propagation time characteristic of the device without the disadvantages associated with simply increasing the speed of all of those resources.
It is yet another object of this invention to improve PLDs with respect to such features as secondary (e.g., clock and clear) signal distribution, input/output circuitry, and circuitry for cascading two or more logic modules together.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing a programmable logic device with interconnection resources that are at least partly constructed in two substantially parallel forms or subsets. The interconnection resources in the first subset are constructed to have what may be termed xe2x80x9cnormalxe2x80x9d signal propagation speed characteristics. The interconnection resources in the substantially parallel second subset are constructed to have significantly faster signal propagation speed characteristics. For example, as compared to the first subset, the second subset may be constructed with larger drivers and pass gates, wider and more widely spaced metal tracks for conductors, and other similar features for increasing signal propagation speed. Where both forms of interconnection resources are provided, most of the resources are preferably of the normal-speed variety and only a minority (e.g., from about 20% to about 33%, most preferably about 25%) are of the high-speed form.
The high-speed interconnection resources are preferably sufficiently extensively provided on the device so that they can be used for at least part of the routing of signals between substantially any two (or more) of the logic regions on the device. (It will be appreciated, of course, that the high-speed resources are likely to be of greatest value and therefore to find the greatest use in making connections between logic regions that are relatively far apart on the device.) Thus interconnections between logic regions in virtually any locations on the device can be made either entirely via the normal-speed interconnection resources or at least partly via the high-speed interconnection resources.
A typical design objective for the high-speed resources is to make it possible to double the speed at which the device can be clocked by providing a sufficient quantity of sufficiently fast high-speed resources so that those resources can be used to convey the signals that give the device its longest signal propagation time and to thereby halve the propagation time of those signals. On the other hand, to avoid the disadvantages of simply trying to greatly increase the speed of all the interconnection resources on the device, only a minor portion of the interconnection resources of any given kind are made high-speed. The major portion remain normal-speed and are used for the bulk of the interconnections that are less speed-critical.
The input/output (xe2x80x9cI/Oxe2x80x9d) circuitry of PLDs may be improved in accordance with the invention by providing rows of I/O cells (including I/O pins) interspersed among the rows of logic and other circuitry on the device. This distributes the I/O pins more uniformly across the device, thereby alleviating I/O pin shortages that can result from having I/O pins only around the periphery of the device. Distributing I/O pins across the device can also facilitate secondary (e.g., clock and clear) signal distribution (e.g., with reduced skew) by allowing such signals to come from I/O pins closer to the center of the device. Secondary signal distribution circuitry can be provided to take advantage of such improved I/O pin distribution. Cascade connections between adjacent or nearby logic regions may be improved to speed up such connections, to increase their utility, and to decrease their burden on the device when they are not being used.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.